Buy BGA Rework Station

Buy BGA Rework Station

1. You can buy BGA Rework Station directly from original manufacturer. 2. DH-A2 Automatic BGA Rework Station. 3. Micrometer for BGA angle adjust and motherboard adjust. 4. Port: Shenzhen.

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Product Details

Buy BGA Rework Station 

bga soldering station

Automatic BGA Soldering Station with optical alignment

1.Application Of Automatic Optical BGA Rework Station 

Work with all kinds of motherboards or PCBA.

Solder, reball, desoldering different kind of chips: BGA,PGA,POP,BQFP,QFN,SOT223,PLCC,TQFP,TDFN,TSOP, PBGA,CPGA,LED chip.

2.Product Features of Automatic Optical BGA Rework Station 

Automatic BGA Soldering Station with optical alignment

 

3.Specification of Automatic Optical BGA Rework Station 

Laser position CCD Camera BGA Reballing Machine

4.Details of Automatic Optical BGA Rework Station 

ic desoldering machine

chip desoldering machine

pcb desoldering machine


5.Why Choose Our Automatic Optical BGA Rework Station

motherboard desoldering machinemobile phone desoldering machine


6.Certificate of Automatic Optical BGA Rework Station 

UL, E-MARK, CCC, FCC, CE ROHS certificates. Meanwhile, to improve and perfect the quality system, Dinghua has passed ISO, GMP, FCCA, C-TPAT on-site audit certification.

pace bga rework station


7.Packing & Shipment of Automatic BGA Rework Station 

Packing Lisk-brochure



8.Shipment for Automatic Optical Reballing BGA Machine

DHL/TNT/FEDEX. If you want other shipping term, please tell us. We will support you.


9. Terms of Payment

Bank transfer, Western Union, Credit Card.

Please tell us if you need other support. 


10. How DH-A2 Automatic BGA IC Reballing Machine work?




11. Related knowledge

About flash chip


Supply dynamics

Recently, SandForce's new owner chip company LSI said that they are developing a new firmware for the SF master SSD in Ultrabook. The main function is to reduce the power consumption of the SSD, and also improve the performance of the SSD and speed up the startup. speed.


parameter

3. 3V power supply;

The internal memory cell array of the chip is (256M + 8.192M) bit × 8bit, and the data register and buffer memory are both (2k + 64) bit × 8bit;

I/O port with instruction/address/data multiplexing;

Program and erase commands can be suspended during power conversion;

Thanks to the reliable CMOS moving gate technology, the chip can achieve a maximum 100kB program/erase cycle, which guarantees data storage for 10 years without loss.


Working status

I/O0~I/O7: data input and output port, I/O port is often used for input of instruction and address and input/output of data, where data is

Enter during the reading process. When the chip is not selected or cannot be output, the I/O port is in a high impedance state.

CLE: The instruction latch is used to activate the instruction to the instruction register path and latch the instruction on the rising edge of WE and CLE is high.

ALE: Address latch, used to activate the path of the address to the internal address register, and the address is latched on the rising edge of WE and ALE is high.

CE: Chip Selector, used to control device selection. When the device is busy, CE is high and ignored, and the device cannot return to the standby state.

RE: Read enable, used to control the continuous output of data and send the data to the I/O bus. The output data is valid only on the falling edge of the RE, and it can also accumulate internal data addresses.

WE: The write enable terminal is used to control the instruction writing of the I/O port. At the same time, the command, address and data can be latched on the rising edge of the WE pulse through this port.

WP: Write protector, which can be write-protected in the power conversion through the WP terminal. When WP is low, its internal high level generator will be reset.

R/ B : Ready/Busy output, the output of R/B can show the operating status of the device. When R/B is low, it indicates that a program, erase or random read operation is in progress. After the operation is completed, R/B will automatically return to high level. Since the terminal is an open-drain output, it will not be in a high-impedance state even when the chip is not selected or the output is disabled.

PRE: Power-on read operation, used to control the automatic read operation when power is on, and the PRE terminal can be connected to VCC to realize the power-on automatic read operation.

VCC: Chip power terminal.

VSS: Chip ground.

NC: Hanging.

Work status editing

1 page read operation

The default state of the flash chip is the read state. The read operation is to start the instruction by writing the 00h address to the instruction register through 4 address cycles. Once the instruction is latched, the read operation cannot be written in the next page.

The data can be randomly output from one page by writing a random data output instruction. The data address can automatically find the next address by random output instructions from the data address to be output. Random data output operations can be used multiple times.

2 page programming

The programming of the flash chip is page-by-page, but it supports multiple partial page programming in a single page programming cycle, while the number of consecutive pages of a partial page is 2112. The program operation can be started by writing to the page program acknowledgment instruction (10h), but continuous data must be input before the instruction (10h) is written.

Continuously loading data After writing a continuous data input instruction (80h), it will start 4 cycles of address input and data loading, but the word is different from the programmed data, it does not need to be loaded. The chip supports random input of data in the page and can automatically change the address according to the random data input command (85h). Random data entry can also be used multiple times.

3 cache programming

Cache programming is a type of page programming that can be performed by a 2112-byte data register and is valid only in one block. Because the flash chip has a page buffer, it can perform continuous data input when the data register is programmed into the memory cell. Cache programming can only begin after the end of an incomplete programming cycle and the data registers are passed from the cache. The internal programming can be judged by the R/B pin. If the system only uses R/B to monitor the progress of the program, then the order of the last page of the target program must be arranged by the current page programming instructions.

4 storage unit dubbing

This effect can quickly and efficiently overwrite the data in a page without accessing the external memory. Since the time spent on continuous access and reloading is shortened, the execution capability of the system is improved. Especially when a part of the block is upgraded and the rest of the block needs to be copied into the new block, its advantages are clearly shown. This operation is a continuously executed read command, but does not require continuous access to and copy of the program from the destination address. A read operation of the original page address instruction of "35h" can transfer the entire 2112 bytes of data to the internal data buffer. When the chip returns to the ready state, the page copy data input instruction with the destination address loop is written. The error program in this operation is given by the "pass/fail" status. However, if the operation takes too long to run, a bit operation error will result due to data loss, resulting in an external error "check/correct" device check failure. For this reason, the operation should be corrected with two errors.

5 block erase

The erase operation of the flash chip is performed on a block basis. The block address load will start with a block erase instruction and be completed in two cycles. In fact, when address lines A12 to A17 are left floating, only address lines A18 to A28 are available. The erase can be started by loading the erase confirmation command and the block address. This operation must be performed in this order to prevent the contents of the memory from being affected by external noise and causing an erase error.

6 read status

A status register within the flash chip confirms that the program and erase operations were completed successfully. After the write instruction (70h) to the instruction register, the read cycle outputs the contents of the status register to the I/O on the falling edge of CE or RE. The instruction register will remain in the read state until the new instruction arrives, so if the status register is in the read state during a random read cycle, then a read instruction should be given before the read cycle begins.


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