Auto Optical BGA Reworl Station

Widely used in chip-level repairing for motherboard of mobile, laptop, computer, TV, air conditioner etc. It has high successful rate of repairing and high degree of automation and save lots of human efforts. We are professional manufacturer of this machine and have this machines available in stock.

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Product Details

Auto Optical BGA Rework Station


1.Application of Auto Optical BGA Rework Station


Motherboard of computer, smart phone, laptop, MacBook logic board,digital camera ,air conditioner, TV and other electronic equipments from medical industry, communication industry, automobile industry, etc.

Suitable for different kind of chips: BGA,PGA,POP,BQFP,QFN,SOT223,PLCC,TQFP,TDFN,TSOP, PBGA,CPGA,LED chip.


2.Product Features of Auto Optical BGA Rework Station

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•High successful rate of chip-level repairing. Desoldering, mounting and soldering process is automatic.

• Precise alignment of every soldering joint can be guaranteed with optical alignment CCD camera.

•Precise temperature control can be ensured with 3 independent heating areas. The machine can set and save 1 million of temperature profile.

• Build-in vacuum in mounting head pick up BGA chip automatically after desoldering completed.


3.Specification of Auto Optical BGA Rework Station

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4.Details of Auto Optical BGA Rework Station

1.CCD camera( precise optical alignment system) ; 2.HD digital display ; 3. Micrometer (adjust angle of chip) ; 4.3 independent heaters ( hot air & infrared ) ; 5. Laser positioning ; 6. HD touch screen interface , PLC control ; 7.Led headlamp ; 8.Joystick control .

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5.Why Choose Our Auto Optical BGA Rework Station?

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6.Certificate of Auto Optical BGA Rework Station

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7.Packing & Shipment of Auto Optical BGA Rework Station

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8.FAQ

How to test the chip?


Initial system-level chip test


The SoC is based on deep submicron processes, so testing new Soc devices requires a completely new approach. Because each functional component has its own testing requirements, the design engineer must make a test plan early in the design process.


The block-by-block test plan for SoC devices must be implemented: properly configured ATPG tools for logic testing; short test times; new high-speed fault models and multiple memory or small array tests. For the production line, the diagnostic method not only finds the fault, but also separates the faulty node from the working node. In addition, test multiplexing techniques should be used whenever possible to save test time. In the field of highly integrated IC testing, ATPG and IDDQ's testable design techniques have a powerful fault separation mechanism.


Other actual parameters that need to be planned in advance include the number of pins that need to be scanned and the amount of memory at each pin end. Boundary scans can be embedded on the SoC, but are not limited to interconnect tests on boards or multi-chip modules.


Although the chip size is decreasing, a chip can still pack millions to 100 million transistors, and the number of test modes has increased to unprecedented levels, resulting in longer test cycles. This problem can be tested. Mode compression to solve, the compression ratio can reach 20% to 60%. For today's large-scale chip design, in order to avoid capacity problems, it is necessary to find test software that can run on 64-bit operating systems.


In addition, test software is faced with new testing problems caused by deep sub-micron processes and increasing frequency. In the past, the ATPG test mode for testing static blocking faults was no longer applicable. Adding functional patterns to traditional tools made it difficult to find new faults. A better approach is to classify past functional mode groups to determine which faults cannot be detected, and then create an ATPG mode to capture these missing fault types.


As design capacity increases and test time per transistor decreases, in order to find speed-related problems and verify circuit timing, a synchronous test method must be employed. Synchronous testing must incorporate multiple fault models, including transient models, path delays, and IDDQ.


Some companies in the industry believe that combining blocking, functional, and transient/path delay faults may be the most effective test strategy. For deep submicron chips and high frequency operation, transient and path delay testing is even more important.


To solve the problem of ATE accuracy when synchronizing the test core and reduce the cost, it is necessary to find a new method that simplifies the interface of the test device (transient and path delay test requires accurate clock at the test device interface), It ensures that the signal is accurate enough during the test.


Since there is a high possibility of manufacturing defects in the SoC memory block, the memory BIST must have a diagnostic function. Once a problem is found, the defective address unit can be mapped to the redundant memory of the spare address unit, and the detected fault address will be discarded. Avoid discarding the entire expensive chip.


Testing small embedded memory blocks eliminates the need for additional gates or control logic. For example, vector conversion testing techniques can convert functional modes into a series of scan modes.


Unlike the BIST method, the functional input of the bypass memory block does not require additional logic. Because no additional test logic is required, SoC development engineers can reuse test patterns that were formed in the past.


Advanced ATPG tools not only test macros in parallel but also determine if there are conflicts, as well as detailing which macros can be tested in parallel and which macros can't be tested in parallel. In addition, these macros can be effectively tested even if the macro clock is the same as the scan clock (such as synchronous memory).


At present, there are not enough test points on the dense double-sided board, and each complex chip must be equipped with a boundary scan circuit. Without boundary scans, board-level manufacturing defect lookups are quite difficult and can't even be found. With boundary scan, board-level testing is extremely easy and independent of the logic circuitry within the chip. Boundary scan can also configure the ATPG mode to the scan chain of the chip at any stage of production.



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